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PI74SSTVF16857A
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
14-Bit Registered Buffer
Product Features
* Designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 * Supports SSTL_2 Class I output specifications * SSTL_2 Input and Output Levels * Designed for DDR Memory * Flow-Through Architecture * Packaging Options (Lead-free packages are available): - 48-pin 240 mil wide plastic TSSOP (A) - 48-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor's PI74SSTVF16857A series of logic circuits are produced using the Company's advanced sub-micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTVF16857A universal bus driver is designed for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off.
R CLK
V
Logic Block Diagram
CLK CLK RESET D1 VREF 38 39 34 48 35
1
Q1
D
Pericom's PI74SSTVF16857A is characterized for operation from 0 to 70C.
Product Pin Configuration
TO 13 OTHER CHANNELS
Product Pin Description
Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF Description Reset (Active Low) Clock Input Clock Input Data Input Data Output Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage
(1)
Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8
1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40
D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14
48-Pin 39 A, K 38 11
37 36 35 34 33 32 31 30 29 28 27 26 25
Truth Table
RESET L H H
Inputs CLK X L or H CLK X L or H D X H L X
Outputs Q L H L Q o( 2 )
Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14
Notes: 2. Output level before the 1. H = High Signal Level indicated steady state L = Low Signal Level input conditions were = Transition LOW-to-HIGH established. = Transition HIGH-to-LOW X = Irrelevant
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PS8687
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PI74SSTVF16857A 14-Bit Registered Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Parame te r Storage Temperature Supply Voltage Input Voltage(1) Output Voltage(1,2) Input Clamp Current Output Clamp Current Continuous Output Current VDD, VDDQ, or GND current/pin Package Thermal Impedance A- Package K- Package Symbol Tstg VDD or VDDQ VI VO II K, VI < 0 IO K, VO < 0 IO, VO = 0 to VDDQ IDD, IDDQ or GND
O JA
Ratings -65 to 150 - 0.5 to 3.6 - 0.5 to VDD + 0.5 - 0.5 to VDDQ + 0.5 - 50 50 50 100 70 58
Units
oC
V
mA
o
C/W
Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
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PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A 14-Bit Registered Buffer
Recommended Operating Conditions
Parame te rs De s cription PC1600 P C 2700 P C 3200 Reference Voltage VREF = 0.5X VDDQ AC input High Voltage AC input Low Voltage Input Voltage DC Input High Voltage DC Input Low Voltage Input High Voltage Input Low Voltage Common- Mode Input Voltage Range Peak- to- Peak Input Voltage High- Level Output Current Low- Level Output Current Operating Free- Air Temperature 0 RESET 1.7 0.7 0.97 0.36 1.53 VDDQ +0.6 -16 16 70 mA C Data Inputs PC1600 P C 2700 P C 3200 Data Inputs Data Inputs 0 VREF +0.15 VREF -0.15 VREF M in. 2.3 2.5 1.15 1.25 VREF +0.31 VREF - 0.31 VDD V Nom. 2.5 2.6 1.25 1.3 M ax. 2.7 2.7 1.35 1.35 Units
VDD/VDDQ
Core/Output Supply Voltage
VREF VIH VIL VI VIH VIL VIH VIL VICR VID IOH IOL TA
CLK,CLK
3
PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A 14-Bit Registered Buffer
DC Electrical Characteristics for PC1600 ~ PC2700
(Over the Operating Range, TA = 0C to +70C, VDD = 2.5V 200mV, VDDQ = 2.5V 200mV)
Pa ra me te rs VIK VO H II = -1 8 mA
Te s t Co nditio ns
VCC 2.3V
M in.
Typ. (1)
M ax. -1.2
Units
IOH = -10 0 A IOH = -8 mA IOL = 10 0 A IOH = 8mA VI = VDD o r GN D RES ET = GN D VI = VIH (AC ) o r VI (AC ), RES ET = VDD RES ET = VDD VI = VIH (AC ) o r VIL(AC ), C K and C K switching 5 0 % d uty cycle RES ET = VDD VI = VIH (AC ) o r VIL(AC ), C K and C K switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle VI = VREF 3 10 mV VIC R= 1. 2 5 V, VI(PP) = 3 6 0 mV VI = VC C o r GN D
2 . 3 V- 2 . 7 V VDD -0 . 2 V 2.3V 2 . 3 V- 2 . 7 V 2.3V 2.7V 1.95 0.2 0.35 5 10 25 A mA A/ clo ck MHz V
VO L II IDD All Inp uts, S tand b y (S tatic) O p erating S tatic Dynamic O p erating C lo ck o nly IDDD Dynamic O p erating - p er each d ata inp ut
28 IO = 0 2.7V
9
A/ clo ck MHz Data 3.5 3.5 3.5 pF
Data inp uts CI C K and C K RES ET
2.5 2.5V 2.5 2.5
Notes: 4. Typical values are at VDD = Nominal VDD, TA = +25C.
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PS8687
05/27/03
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PI74SSTVF16857A 14-Bit Registered Buffer
DC Electrical Characteristics for PC3200
(Over the Operating Range, TA = 0C to +70C, VDD = 2.6V 100mV, VDDQ = 2.6V 100mV)
Pa ra me te rs VIK VO H II = -1 8 mA
Te s t Co nditio ns
VCC 2.5V
M in.
Typ. (1)
M ax. -1.2
Units
IOH = -10 0 A IOH = -8 mA IOL = 10 0 A IOH = 8mA VI = VDD o r GN D RES ET = GN D VI = VIH (AC ) o r VI (AC ), RES ET = VDD RES ET = VDD VI = VIH (AC ) o r VIL(AC ), C K and C K switching 5 0 % d uty cycle RES ET = VDD VI = VIH (AC ) o r VIL(AC ), C K and C K switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle VI = VREF 3 10 mV VIC R= 1. 2 5 V, VI(PP) = 3 6 0 mV VI = VC C o r GN D
2 . 5 V- 2 . 7 V VDD -0 . 2 V 2.5V 2 . 5 V- 2 . 7 V 2.5V 2.7V 1.95 0.2 0.35 5 10 25 A mA A/ clo ck MHz V
VO L II IDD All Inp uts, S tand b y (S tatic) O p erating S tatic Dynamic O p erating C lo ck o nly IDDD Dynamic O p erating - p er each d ata inp ut
28 IO = 0 2.7V
9
A/ clo ck MHz Data 3.5 3.5 3.5 pF
Data inp uts CI C K and C K RES ET
2.5 2.6V 2.5 2.5
Notes: 4. Typical values are at VDD = Nominal VDD, TA = +25C.
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PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A 14-Bit Registered Buffer
Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
VDD =2 .5 V 0 . 2 V M in. fclo ck tW ta c t tinact tS U C lo ck F req uency P ulse Duratio n Differential inp uts active time (5) O utp ut slew rate d ifferential inp uts inactive time(6) Data b efo re C K , C K
VDD =2 .6 V 0 . 1 V M in. M ax. 270 2.5
M ax. 270
Units MHz
2.5 22 22 0.75 0.9 0.75 0.9
22 22 0.75 0.9 0.75 0.9 ns
S etup time, fast slew rate(7, 9) S etup time, slo w slew rate(8, 9) Ho ld time , fast slew rate(7, 9) Ho ld time, slo w slew rate(8, 9)
th
Data b efo re C K , C K
Notes: 5. Data inputs must be held low for a minimum time of tact min , after RESET is taken high 6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low. 7. Data signal input slew rate 1 V/ns 8. Data signal input slew rate 0.5V/ns and <1V/ns 9. CLK, CLK input slew rates are 1 V/ns.
Switching Characteristics for PC1600 ~ PC2700
(over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms).
Parame te r fmax tpd tphl CLK, CLK RESET Q Q From (Input) To (Output) VDD = 2.5V 0.2V M in. 210 1.1 1.8 5.0 Typ. M ax. Units MHz ns
Switching Characteristics for PC3200
(over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms).
Parame te r fmax tpd tphl CLK, CLK RESET Q Q From (Input) To (Output) VDD = 2.6V 0.1V M in. 210 1.1 1.8 5.0 Typ. M ax. Units MHz ns
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PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A 14-Bit Registered Buffer
Test Circuit and Switching Waveforms
LVCMOS RESET Input
VDD/2
VDD 0V
From Output Under Test 500
Test Point CL = 30pF(8)
t inact
IDD(9) 10%
tact
90% IDDH IDDL
Load Circuit
Voltage and Current Waveforms Input Active and Inactive Times
Timing Input
VICR t PLH
VICR t PHL VTT
VI(PP)
tw
VIH Input VREF VREF VIL
Output
VOH VOL
VTT
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Propagation Delay Times
Timing Input tsu Input
VREF
VICR
VI(PP)
th
VIH VREF VIL
LVCMOS RESET Input
VDD/2 t PHL
VIH VIL VOH VTT VOL
Output
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information
Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50. Input slew rate = 1V/ns 20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF - 310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd.
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PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A 14-Bit Registered Buffer
48-Pin TSSOP Package (A)
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
48-Pin TSSOP Package (K)
48
.169 .177
4.30 4.50 .0035 .008 0.09 0.20
1
.378 9.60 .386 9.80
.031 .041 0.80 1.05
0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.016 BSC 0.40
.0051 .009 0.13 0.23
.002 .006 0.05 0.15
Max. .047 1.20
Ordering Information
Orde ring Code PI74SSTVF16857AA PI74SSTVF16857AAE PI74SSTVF16857AK PI74SSTVF16857AKE
Notes: X = tape/reel; E = Pb-free
Package Code A A K K
Package Type 48- Pin 240- mil TSSOP Pb- free 48- Pin 240- mil TSSOP 48- Pin 173- mil TVSOP Pb- free 48- Pin 173- mil TVSOP
Ope rating Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8687 05/27/03

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